Rapita Systems Ltd

First Code Coverage Solution for Multi-Core Systems Announced by Rapita Systems Munich, 25th March 2015 Rapita Systems Ltd, leading provider of on-target verification solutions for critical, real-time embedded systems, is pleased to announce the...

VeTeSS (Verification and Testing to Support Functional Safety Standards) is a €20m three-year pan-European research project designed to create innovative technologies to improve the verification of the safety of these embedded systems.

Rapita Systems Ltd is pleased to announce availability of a new version of RVS. This new version introduces RapiTask, which provides visualization of scheduling and event tracing for single and multi-core embedded systems

Over the next decade, the embedded software industry will face a massive transition to multicore and manycore processors.

Rapita Systems are demonstrating Rewind, an innovative debug support feature for RapiTime, at the Avionics Exhibition. This technology allows developers to track execution forwards and backwards in recorded traces of embedded real-time applications.

Rapita Systems will be demonstrating a “zero overhead instrumentation” approach for timing analysis & code coverage at Embedded World. This technology allows developers to analyze embedded applications with no additional code for instrumentation.

Rapita Systems announces that it is launching a beta program for new C++ support. Avionic software developers using C++ will be able to use RapiTime to: measure execution times, code coverage, and worst-case execution times for their applications.

Rapita Systems Ltd. today announced the latest release of version 2.2 of its on-target real-time profiling/timing analysis toolset. RapiTime is aimed at engineers developing real-time, embedded software.

Rapita Systems announces the availability of the RTBx real-time data logger family. RTBx makes it easy to collect execution time data from virtually any embedded, real-time target with minimal impact on the execution time of the application.