Centellax, Inc.

Centellax delivered the first shipments of their recently-released 32 Gb/s Stressed Serial BERT Solution (model #SSB32) in November and feedback from customers has been exceedingly well-received.

David Ferguson, Principal Characterization Engineer at Xilinx San Jose, selected the Centellax SSB32J Stressed Serial BERT as his new test solution after a thorough evaluation of the competitive offerings.

New 3-32 Gb/s Stressed Serial BERT Solution for serial data test requirements for 100 Gigabit Ethernet (100GbE) standards, compliance testing for 4-32G Fibre Channel and InfiniBand EDR/FDR standards, as well as SerDes testing for communication ICs.

Centellax announced today the release of a new 3-17G Stressed Serial BERT Solution (model #SSB17) intended for testing to 16x Fibre Channel (16GFC) and 14G InfiniBand FDR standards.

Santa Rosa, Calif., April 8, 2011 - Centellax announced today they will be partnering with EDN for a live webcast on optimizing parallel jitter tolerance measurements in multi-lane channels and devices with multiple SERDES.

Centellax announced today the release of their new SCS16000 series of compact 16 Gb/s stressed clock synthesizers. One option includes two tone sinusoidal jitter, true random jitter injection, and spread spectrum clock modulation capabilities.

Centellax announced today the release of their new Centellax Signal Integrity Studio (SIS) application, Version 1.0. SIS provides Centellax customers the ability to control multiple instruments through a Windows-based Graphical User Interface (GUI).

Centellax announced today they will be partnering with EDN China to give a live webcast in Mandarin Chinese, on Characterizing Crosstalk in High-Density, High-Speed Backplanes. The webcast will outline the detrimental effects of crosstalk.